Semiconductor device and manufacturing method thereof

ABSTRACT

A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation of U.S. application Ser. No.16/102,317 filed Aug. 13, 2018, now U.S. Pat. No. 11,049,970, which is adivisional of U.S. application Ser. No. 14/809,158, filed Jul. 24, 2015,now U.S. Pat. No. 10,050,147, the entire contents of each of which isincorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to a semiconductor integrated circuit, and moreparticularly to a semiconductor device having a fin structure and itsmanufacturing process.

BACKGROUND

As the semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,and lower costs, challenges from both fabrication and design issues haveresulted in the development of three-dimensional designs, such as a finfield effect transistor (Fin FET). Fin FET devices typically includesemiconductor fins with high aspect ratios and in which channel andsource/drain (S/D) regions of semiconductor transistor devices areformed. A gate is formed over and along the sides of the fin structure(e.g., wrapping) utilizing the advantage of the increased surface areaof the channel and S/D regions to produce faster, more reliable andbetter-controlled semiconductor transistor devices. In some devices,strained materials in S/D portions of the Fin FET utilizing, forexample, silicon germanium (SiGe), silicon carbide (SiC), and/or siliconphosphide (SiP) may be used to enhance carrier mobility.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIGS. 1A-8B show exemplary sequential processes for manufacturing theFin FET device according to one embodiment of the present disclosure.

FIGS. 9-15B show exemplary sequential processes for manufacturing theFin FET device according to another embodiment of the presentdisclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific embodiments or examples of components andarrangements are described below to simplify the present disclosure.These are, of course, merely examples and are not intended to belimiting. For example, dimensions of elements are not limited to thedisclosed range or values, but may depend upon process conditions and/ordesired properties of the device. Moreover, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Variousfeatures may be arbitrarily drawn in different scales for simplicity andclarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. In addition, the term“made of” may mean either “comprising” or “consisting of.”

As noted above, a gate is formed over and along the sides of the finstructure (e.g., wrapping) utilizing the advantage of the increasedsurface area of the channel and S/D regions to produce faster, morereliable and better-controlled semiconductor transistor devices. Oneprocess of implementing the gate is termed a “gate last” or “replacementgate” methodology. In such a process, a dummy (e.g., polysilicon) gateis initially formed, various processes associated with the semiconductordevice are performed, and the dummy gate is subsequently removed andreplaced with a gate (e.g., metal gate). During the process of removingthe dummy gate, a region in spacer dielectric regions below spacerelements adjacent the dummy gate may be narrowed. Strained materials inS/D portions may be removed due to the narrower region of spacerdielectric regions, thus creating gate to S/D encroachment and poorisolation.

FIGS. 1A-8B show exemplary processes for manufacturing a semiconductorFET device having a fin structure (Fin FET). It is understood thatadditional operations can be provided before, during, and afteroperations shown by FIGS. 1A-8B, and some of the operations describedbelow can be replaced or eliminated, for additional embodiments of themethod. The order of the operations may be interchangeable.

As shown in FIG. 1A, fin structures are fabricated over a core regionand over a peripheral region on a substrate. In some embodiments, thecore region refers to a part of a core circuit in an electronic systemthat primarily performs logical operations, and the peripheral regionrefers to a part of a peripheral circuit (e.g., I/O circuit) in theelectronic system that performs, for example, data input and data outputoperations. FIG. 1A is an exemplary perspective view of the Fin FETdevice at one of the various stages of the fabrication process accordingto one embodiment. FIG. 1B is an exemplary cross sectional view alongthe line a-a of FIG. 1A.

A fin structure 12 includes a first fin structure 121 corresponding to acore region and a second fin structure 122 corresponding to a peripheralregion. Although the first fin structure 121 and the second finstructure 122 are disposed adjacent each other (as part of the same finstructure 12) in FIG. 1A for an illustrative purpose, they are notnecessarily disposed adjacent each other, and the first fin structure121 and the second fin structure 122 may be disposed in differentregions and separately formed in a semiconductor device. The finstructure 12 is formed over a substrate 10 and protrudes from anisolation insulating layer 11. To fabricate a fin structure, a masklayer is formed over the substrate 10 by, for example, a thermaloxidation process and/or a chemical vapor deposition (CVD) process. Thesubstrate 10 is, for example, a p-type silicon substrate. In otherembodiments, the substrate 10 is an n-type silicon substrate. The masklayer includes, for example, a pad oxide (e.g., silicon oxide) layer anda silicon nitride mask layer in some embodiments.

Alternatively, the substrate 10 may comprise another elementarysemiconductor, such as germanium; a compound semiconductor includingIV-IV compound semiconductors such as SiC and SiGe, III-V compoundsemiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN,AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.In one embodiment, the substrate 10 is a silicon layer of an SOI(silicon-on insulator) substrate. When an SOI substrate is used, the finstructure may protrude from the silicon layer of the SOI substrate ormay protrude from the insulator layer of the SOI substrate. In thelatter case, the silicon layer of the SOI substrate is used to form thefin structure. Amorphous substrates, such as amorphous Si or amorphousSiC, or insulating material, such as silicon oxide may also be used asthe substrate 10. The substrate 10 may include various regions that havebeen suitably doped with impurities (e.g., p-type or n-typeconductivity).

In this embodiment, a bulk silicon wafer is used as a starting materialand constitutes the substrate 10. However, in some embodiments, othertypes of substrate may be used as the substrate 10. For example, asilicon-on-insulator (SOI) wafer may be used as a starting material, andthe insulator layer of the SOI wafer constitutes the substrate 10 andthe silicon layer of the SOI wafer is used for the fin structure 12.

The pad oxide layer may be formed by using thermal oxidation or a CVDprocess. The silicon nitride mask layer may be formed by a physicalvapor deposition (PVD), such as a sputtering method, a CVD,plasma-enhanced chemical vapor deposition (PECVD), an atmosphericpressure chemical vapor deposition (APCVD), a low-pressure CVD (LPCVD),a high density plasma CVD (HDPCVD), an atomic layer deposition (ALD),and/or other processes.

The thickness of the pad oxide layer is in a range of about 2 nm toabout 15 nm and the thickness of the silicon nitride mask layer is in arange of about 2 nm to about 50 nm in some embodiments. A mask patternis further formed over the mask layer. The mask pattern is, for example,a resist pattern formed by lithography operations.

By using the mask pattern as an etching mask, a hard mask pattern of thepad oxide layer and the silicon nitride mask layer is formed. The widthof the hard mask pattern is in a range of about 5 nm to about 40 nm insome embodiments. In certain embodiments, the width of the hard maskpatterns is in a range of about 7 nm to about 12 nm.

By using the hard mask pattern as an etching mask, the substrate 10 ispatterned into fin structure 12 by trench etching using a dry etchingmethod and/or a wet etching method. A height (Ht) of the fin structure12 is in a range of about 20 nm to about 300 nm. In certain embodiments,the height is in a range of about 30 nm to about 150 nm. When theheights of the fin structures are not uniform, the height from thesubstrate may be measured from the plane that corresponds to the averageheights of the fin structures. The width of the fin structure 12 is in arange of about 5 nm to 15 nm.

As shown in FIG. 1A, one fin structure 12 extends in the Y direction.However, the number of the fin structures is not limited to one. Thenumber may be two, three, four or five or more. In addition, one or moredummy fin structures may be disposed adjacent both sides of the finstructure 12 to improve pattern fidelity in patterning processes. Thewidth of the fin structure 12 is in a range of about 4 nm to about 40 nmin some embodiments, and may be in a range of about 5 nm to about 15 nmin certain embodiments. The height (Ht) of the fin structure 12 is in arange of about 20 nm to about 300 nm in some embodiments, and may be ina range of about 30 nm to 150 nm in other embodiments. One skilled inthe art will realize, however, that the dimensions and values recitedthroughout the descriptions are merely examples, and may be changed tosuit different scales of integrated circuits.

After forming the fin structure, an isolation insulating layer 11 isformed over the fin structure 12. The isolation insulating layer 11includes one or more layers of insulating materials such as siliconoxide, silicon oxynitride or silicon nitride, formed by LPCVD (lowpressure chemical vapor deposition), plasma-CVD or flowable CVD. In theflowable CVD, flowable dielectric materials instead of silicon oxide aredeposited. Flowable dielectric materials, as their name suggests, can“flow” during deposition to fill gaps or spaces with a high aspectratio. Usually, various chemistries are added to silicon-containingprecursors to allow the deposited film to flow. In some embodiments,nitrogen hydride bonds are added. Examples of flowable dielectricprecursors, particularly flowable silicon oxide precursors, include asilicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogensilsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), aperhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or asilyl-amine, such as trisilylamine (TSA). These flowable silicon oxidematerials are formed in a multiple-operation process. After the flowablefilm is deposited, it is cured and then annealed to remove undesiredelement(s) to form silicon oxide. When the undesired element(s) areremoved, the flowable film densifies and shrinks. In some embodiments,multiple anneal processes are conducted.

The flowable film is cured and annealed more than once. The flowablefilm may be doped with boron and/or phosphorous. The isolationinsulating layer 11 may be formed by one or more layers of SOG, SiO,SiON, SiOCN and/or fluoride-doped silicate glass (FSG) in someembodiments.

After forming the isolation insulating layer 11 over the fin structure12, a planarization operation is performed so as to remove part of theisolation insulating layer 11 and the mask layer (the pad oxide layerand the silicon nitride mask layer). The planarization operation mayinclude a chemical mechanical polishing (CMP) and/or an etch-backprocess. Then, the isolation insulating layer 11 is further removed sothat an upper part of the fin structure 12, which is to become a channellayer 12A, is exposed, as shown in FIG. 1A.

In certain embodiments, the partially removing of the isolationinsulating layer 11 may be performed using a wet etching process, forexample, by dipping the substrate in hydrofluoric acid (HF). In otherembodiments, the partially removing the isolation insulating layer 11may be performed using a dry etching process. For example, a dry etchingprocess using CHF₃ or BF₃ as etching gases may be used.

After forming the isolation insulating layer 11, a thermal process, forexample, an anneal process, may be performed to improve the quality ofthe isolation insulating layer 11. In certain embodiments, the thermalprocess is performed by using rapid thermal annealing (RTA) at atemperature in a range of about 900° C. to about 1050° C. for about 1.5seconds to about 10 seconds in an inert gas ambient, such as an N₂, Aror He ambient.

First dummy gate structure 60 and second dummy gate structure 60B areformed as shown in FIGS. 1A and 1B.

A dielectric layer 20 and a poly silicon layer are formed over theisolation insulating layer 11 and the exposed fin structure 12, and thenpatterning operations are performed so as to obtain a first dummy gatestructure 60 and a second dummy gate structure 60B. The first dummy gatestructure 60 includes a first dummy gate electrode layer 50 made of polysilicon and a dummy gate dielectric region 20A. The second dummy gate60B includes a second dummy gate electrode layer 50B made of polysilicon and a dummy gate dielectric region 20B.

The patterning of the poly silicon layer in the first dummy gatestructure 60 is performed by using a hard mask 32 including two layers30, 40 in some embodiments. In some embodiments, the first layer 30 maybe a silicon oxide layer and the second layer 40 may be a siliconnitride layer. In other embodiments, the first layer 30 may be a siliconnitride layer and the second layer 40 may be a silicon oxide layer. Thepatterning of the poly silicon layer in the second dummy gate structure60B is also performed by using a hard mask 32B including a siliconnitride layer 40B and a silicon oxide layer 30B in some embodiments. Inother embodiments, the order of the silicon nitride and silicon oxidelayers may be reversed.

The dummy gate dielectric layer 20 may be silicon oxide formed bythermal oxidation, CVD, PVD, ALD, e-beam evaporation, or other suitableprocess. In some embodiments, the dielectric layer 20 may include one ormore layers of high-k dielectrics, such as hafnium oxide (HfO₂). High-kdielectrics comprise metal oxides. Examples of metal oxides used forhigh-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf,Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/ormixtures thereof. In some embodiments, a thickness of the gatedielectric layer 20 is in a range of about 3 nm to about 4 nm. That is,the height (H) of the dummy gate dielectric region 20A is in a range ofabout 3 nm to about 4 nm. The dummy gate dielectric region 20A isdefined by a first sidewall and a second sidewall of the first dummygate structure 60, and the first sidewall and second sidewall extendsubstantially perpendicular to a top surface of the dielectric layer 20.That is, the width (W2) of the dummy gate dielectric region 20A is thesame as the width (W1) of the dummy gate electrode layer 50.

In some embodiments, the first and second dummy gate electrode layers50, 50B may comprise a single layer or multilayer structure. The firstand second dummy gate electrode layers 50, 50B may include polysiliconand/or other suitable layers. The first and second dummy gate electrodelayers 50, 50B may be formed by depositing a layer of polysilicon. Thelayer of polysilicon may then be patterned and etched into a polysilicongate electrode. The first and second dummy gate electrode layers 50, 50Bmay be formed using a suitable process such as ALD, CVD, PVD, plating,patterning or combinations thereof. In the present embodiment, the widthof the first and second dummy gate electrode layer 50, 50B is in therange of about 20 nm to about 300 nm. In some embodiments, a thicknessof the first and second dummy gate electrode layer 50, 50B is in a rangeof about 25 nm to about 240 nm. The width (W3) of the second dummy gateelectrode layer 50B is greater than that of the first dummy gateelectrode layer 50 in some embodiments.

As shown in FIG. 2, a portion of the dielectric layer 20 is partiallyetched using an etching process (wet etch, dry etch, plasma etch, etc.)that is selective to the hard mask 32 to form a dielectric etch backregion 22. The dielectric etch back region 22 is a region other than thedummy gate dielectric region 20A and the gate dielectric region 20B andis adjacent the dummy gate dielectric region 20A and the gate dielectricregion 20B. The etching process may include removal of the dielectriclayer 20 by one or more etching cycles. Each etching cycle may includeremoval of 0.5 nm to 1 nm of the dielectric layer. The total thicknessof the dielectric layer 20 that is removed is in a range of about 1 nmto about 3 nm. That is, the difference between the height (H) of thedummy gate dielectric region 20A or the gate dielectric region 20B andthe height (h) of the dielectric etch back region 22 is in a range ofabout 1 nm to about 3 nm. In some embodiments, a surface treatmentprocess may be performed in the dielectric etch back region 22, such asoxidation, nitridation or ion implantation (e.g., carbon ions).

As shown in FIG. 3, spacer elements 70A, 70B, 71A and 71B are formedover the dummy gate structures 60 and 60B, respectively, and on aportion of the dielectric etch back region 22. The spacer elements 70Aand 70B include two layers of spacer element layers in this embodiment.The thickness of a spacer element layer may be between approximately 2nm and approximately 5 nm. In other embodiments, the spacer elementlayer may be greater than approximately 5 nm in thickness. The number ofspacer element layers is not limited to two. The number may be one,three, four or five or more. The spacer elements 70A and 70B aredisposed adjacent both major vertical sides of the dummy gate structure60, such as the first sidewall 60S1 and second sidewall 60S2,respectively. Spacer elements 70A and 70B are disposed facing sourceregion 80A and drain region 80B, respectively. The spacer element layermay include one or more layers of silicon nitride, silicon oxide,silicon oxynitride, SiCN, SiOCN, and/or other suitable dielectricmaterials. The materials of the two layers of the spacer element layersmay be different in some embodiments, and may be the same in otherembodiments.

In some embodiments, the spacer elements 71A and 71B are formed inaccordance with the details described with reference to the spacerelements 70A and 70B, respectively. In some embodiments, the spacerelements 71A and 71B are simultaneously formed by the same operations asthe spacer elements 70A and 70B. Spacer elements 71A and 71B aredisposed adjacent both major vertical sides of the second dummy gatestructure 60B, such as a third sidewall 61S1 and a fourth sidewall 61S2,respectively. Spacer elements 71A and 71B are disposed facing sourceregion 80C and drain region 80D, respectively.

A spacer dielectric region 22A is defined by a first sidewall and asecond sidewall of the spacer element 70A, and the first sidewall andsecond sidewall extend substantially perpendicular to a top surface ofthe spacer dielectric region 22A. A spacer dielectric region 22B, isdefined by a first sidewall and a second sidewall of the spacer element70B, and the first sidewall and second sidewall extend substantiallyperpendicular to a top surface of the spacer dielectric region 22B. Thatis, the width of the spacer dielectric region 22A or 22B is equal to orless than the width of the spacer element 70A or 70B, respectively.

Similarly, a spacer dielectric region 22C is defined by a first sidewalland a second sidewall of the spacer element 71A, and the first sidewalland second sidewall extend substantially perpendicular to a top surfaceof the spacer dielectric region 22C. A spacer dielectric region 22D isdefined by a first sidewall and a second sidewall of the spacer element71B, and the first sidewall and second sidewall extend substantiallyperpendicular to a top surface of the spacer dielectric region 22D. Thatis, the width of the spacer dielectric region 22C or 22D is equal to orless than the width of the spacer element 71A or 71B, respectively.

The first fin structure 121 and the second fin structure 122 in FIG. 3are subsequently etched down to form one or more recessed portions (notshown). In some embodiments, using the pair of spacer elements 70A and70B (and the first dummy gate structure 60) as hard masks, a biasedetching process is performed to recess a top surface of the channellayer 12A that is unprotected or exposed to form the recessed portionsof the first fin structure 121. Similarly, using the pair of spacerelements 71A and 71B (and the second dummy gate structure 60B) as hardmasks, a biased etching process is performed to recess a top surface ofthe channel layer 12A that is unprotected or exposed to form therecessed portions of the first fin structure 122.

As shown in FIG. 3, a strained material may be selectively grown overthe recessed portions and extend over the top surface of the channellayer 12A. In at least one embodiment, the strained material, such assilicon carbide (SiC) and SiP, is epi-grown by a LPCVD process to formthe source region 80A or 80C and drain region 80B or 80D when the FinFET is an n-type Fin FET. In at least another embodiment, the strainedmaterial, such as silicon germanium (SiGe), is epi-grown by a LPCVDprocess to form the source region 80A or 80C and drain region 80B or 80Dwhen the Fin FET is a p-type Fin FET. The general operations formanufacturing a recessed S/D structure with strain materials (orstressor) in the fin structure are disclosed in U.S. Pat. No. 8,440,517,the entire contents of which are incorporated herein by reference.

As shown in FIG. 4, additional spacer element layers 70C and 70D may beformed adjacent the spacer elements 70A and 70B, such as adjacentsidewalls 60S3 and 60S4, respectively. The additional spacer elementlayers 70C and 70D are formed after the source regions 80A and 80B areformed. The additional spacer element layers 70C and 70D may be formedusing the same material and the same operations for forming the spacerelement layers in spacer elements 70A and 70B, as discussed withreference to FIG. 3. The thickness of additional spacer element layermay be between approximately 2 nm and approximately 5 nm. In otherembodiments, the thickness of the additional spacer element layers 70Cand 70D may be greater than 5 nm. The number of additional spacerelement layers is not limited to two. The number may be one, three, fouror five or more. In addition, the additional spacer element layers 70Cand 70D are disposed adjacent both main sides of the dummy gateelectrode 50. The additional spacer element layer may include one ormore layers of silicon nitride, silicon oxide, silicon oxynitride, SiCN,SiOCN, and/or other suitable dielectric materials. In some embodiments,the additional spacer element layer 70C may be formed before the sourceregion 80A is formed. The additional spacer element layer 70D is formedafter the drain region 80B is formed.

In some embodiments, additional spacer element layers 71C and 71D areformed in accordance with the details described with reference to theadditional spacer element layers 70C and 70D, respectively. In someembodiments, the additional spacer element layers 71C and 71D are formedby the same operations as the additional spacer element layers 70C and70D.

In some embodiments, an inter-layer dielectric (ILD) layer 90 may beformed over a portion of the channel layer 12A, the source regions 80A,80C and the drain regions 80B, 80D. The ILD layer 90 may be formed bychemical vapor deposition (CVD), high density plasma CVD (HDP-CVD),spin-on deposition, physical vapor deposition (PVD or sputtering), orother suitable methods. The ILD layer 90 may include silicon oxide,silicon oxynitride, a low-k material, and/or other suitable dielectric.The ILD layer 90 may be formed on and surrounding the first dummy gatestructure 60 and the second dummy gate structure 60B. The ILD layer 90may be conformably deposited and a chemical mechanical polish (CMP)process performed to planarize the material. The first dummy gatestructure 60 and the second dummy gate structure 60B may serve as aplanarization stopper for the CMP process. In other words, the CMPprocess may be stopped at the exposure of the top surface of the firstdummy gate structure 60 and the second dummy gate structure 60B. In someembodiments, the hard mask 32 and part of the spacer elements 70A,70Band/or additional spacer element layers 70C, 70D are removed from thefirst dummy gate structure 60 by the CMP process. In some embodiments,the hard mask 32B and part of the spacer elements 71A, 71B and/oradditional spacer element layers 71C, 71D are removed from the seconddummy gate structure 60B by the CMP process.

As shown in FIGS. 5-6, the first dummy gate structure 60 is removed. Thefirst dummy gate structure 60 removal may include removing the dummygate electrode 50 as shown in FIG. 5 and the dummy gate dielectricregion 20A as shown in FIG. 6. The removal of the first dummy gatestructure 60 provides an opening between the spacer element 70A and thespacer element 70B within which a metal gate will be formed, as istypically performed in a replacement gate process. The dummy gateelectrode 50 may be removed by an etching solution such as, for example,aqueous ammonia, and/or other suitable etchant. In an alternativeembodiment, the dummy gate electrode 50 may be removed by a suitable dryetching process. Exemplary etchants include chlorine based etchants.

In some embodiments, the dummy gate dielectric region 20A may be removedusing an etching process (wet etch, dry etch, plasma etch, etc.). Theremoval of the dummy gate dielectric region 20A may expose a top surfaceof the channel layer 12A. It is noted that the spacer dielectric region22A and 22B remain on the channel layer 12A underlying the spacerelement 70A and the spacer element 70B respectively.

As shown in FIGS. 5-6, a part of the second dummy gate structure 60B isremoved. The second dummy gate structure 60B removal may includeremoving the dummy gate electrode 50B as shown in FIG. 5. The dummy gateelectrode 50B may be removed by an etching solution such as, forexample, aqueous ammonia, and/or other suitable etchant. In analternative embodiment, the dummy gate electrode 50B may be removed by asuitable dry etching process. Example etchants include chlorine basedetchants. In some embodiments, the gate dielectric region 20B remains onthe channel layer 12A and the spacer dielectric region 22C and 22Dremain on the channel layer 12A underlying the spacer element 71A andthe spacer element 71B respectively.

As shown in FIG. 7, gate structures are formed in the opening providedby the removal of the first dummy gate structure 60 and the part of thesecond dummy gate structure 60B to form Fin FET devices 100 and 200.FIG. 8A is an exemplary planar view of a Fin FET device 100 disposed ina core region as shown in FIG. 7. FIG. 8B is an exemplary planar view ofa Fin FET device 200 disposed in a peripheral region as shown in FIG. 7.In one embodiment, the gate structure of the Fin FET device 100 includesan interfacial layer 110, a high-k dielectric layer 120, a metal layer140 and/or other suitable materials for a gate structure. In oneembodiment, the gate structure of the Fin FET device 200 includes thedielectric region 20B, a high-k dielectric layer 120B, a metal layer140B and/or other suitable materials for a gate structure. In otherembodiments, the gate structure of the Fin FET device 100 or 200 mayfurther include capping layers, etch stop layers, and/or other suitablematerials. The interfacial layer 110 may include a dielectric materialsuch as silicon oxide layer (SiO₂). The interfacial layer 110 may beformed by chemical oxidation, thermal oxidation, atomic layer deposition(ALD), CVD, and/or other suitable processes.

In some embodiments, the high-k dielectric layers 120 and 120B maycomprise one or more layers of metal oxides. Examples of metal oxidesused for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y,Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu,and/or mixtures thereof. In this embodiment, hafnium oxide (HfO₂) isused. The high-k dielectric layers 120 and 120B may be formed by atomiclayer deposition (ALD), chemical vapor deposition (CVD), physical vapordeposition (PVD), and/or other suitable methods.

The metal layers 140 and 140B may include one or more layers of Al, Cu,W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, other conductivematerials with a work function compatible with the substrate material,or combinations thereof. The metal layers 140 and 140B may be formed byCVD, PVD, plating, and/or other suitable processes. One or more CMPprocesses may be performed during the formation of the gate structure.

In some embodiments, the gate voltage of the Fin FET 200 may be higherthan that of the Fin FET 100, which requires the gate dielectric layer20B of the Fin FET 200 to be thicker than the interfacial layer 110 ofthe Fin FET 100.

It is understood that the structures shown in FIGS. 1A-8B may undergofurther CMOS processes to form various features such as contacts/vias,interconnect metal layers, dielectric layers, passivation layers, etc.

FIGS. 9-15B show another embodiment of the present disclosure. In theprevious embodiment, a portion of the dielectric layer 20 is etchedusing an etching process to form the dielectric etch back region 22including spacer dielectric regions 22A, 22B, 22C and 22D as shown inFIGS. 2-3.

Instead of etching a portion of the dielectric layer 20, no etching isperformed on the dielectric layer 20 as shown in FIG. 9. That is, thereis no difference between the height of the dummy gate dielectric region20A and the height of the spacer dielectric region 20C or 20D. There isno difference between the height of the gate dielectric region 20B andthe height of the spacer dielectric region 20E or 20F.

In one embodiment, the height (h) of the spacer dielectric regions 20C,20D, 20E, 20F and the gate dielectric regions 20A, 20B is in a range ofabout 1 nm to 3 nm.

In some embodiments, source regions 81A, 81C, drain regions 81B, 81D,spacer elements 72A, 72B, and spacer elements 73A, 73B as shown in FIG.9 may be formed in accordance with the details described with referenceto FIG. 3. Subsequently, as shown in FIG. 10, the dummy gate electrodelayer 50, 50B, ILD layer 90, and additional spacer element layers 72C,72D, 73C and 73D may be formed and processed in accordance with thedetails described with reference to FIG. 4. As shown in FIG. 11, thedummy gate electrode layer 50 and 50B in FIG. 10 may be removed inaccordance with the details described with reference to FIG. 5. As shownin FIG. 12, a multi-layer (e.g., bi-layer) structure of dielectriclayers 21 is deposited on the dummy gate dielectric region 20A. Amulti-layer (e.g., bi-layer) structure of dielectric layers 21B isdeposited on the gate dielectric region 20B. Dielectric layers 21, 21Bmay include silicon oxide formed by thermal oxidation, CVD, PVD, ALD,e-beam evaporation, or other suitable process. In one embodiment, thethickness of the dielectric layers 21, 21B is in a range of about 1 nmto about 3 nm. In some embodiments, the dielectric layers 21, 21B mayinclude a single dielectric layer. In some embodiments, a surfacetreatment process may be performed on a portion of the dielectric layer20 not covered by the dummy gate electrode layer 50, 50B, such asincluding the spacer dielectric regions 20C, 20D, 20E, 20F, beforeforming the source regions 81A, 81C, drain regions 81B, 81D, spacerelements 72A, 72B, and spacer elements 73A, 73B.

As shown in FIG. 13, the dummy gate dielectric region 20A and thedielectric layers 21 are removed using an etching process (wet etch, dryetch, plasma etch, etc.). The removal of the dummy gate dielectricregion 20A may expose a top surface of the channel layer 12A. It isnoted that the spacer dielectric region 20C and 20D remain on thechannel layer 12A underlying the spacer element 72C and the spacerelement 72D respectively. As shown in FIG. 13, the dielectric layer 21Bremains on the dielectric region 20B. As shown in FIG. 14, a gatestructure is formed in the opening provided by the removal of the firstdummy gate structure 60 to form a Fin FET 100A in accordance with thedetails described with reference to FIG. 7. The gate structure mayinclude an interfacial layer 111, a high-k dielectric layer 121, a metallayer 141 and/or other suitable materials for a gate structure. A gatestructure including the metal layer 141B and the high-k dielectric layer121B of a Fin FET 200A is formed in accordance with the detailsdescribed with reference to FIG. 7.

It is understood that the device shown in FIGS. 9-14B may undergofurther CMOS processes to form various features such as contacts/vias,interconnect metal layers, dielectric layers, passivation layers, etc.

In some embodiments, the gate voltage of the Fin FET 200A may be higherthan the Fin FET 100A, which requires the height of the gate dielectriclayer 20B and the dielectric layer 21B of the Fin FET 200A to be thickerthan interfacial layer 111 of the Fin FET 100A. FIG. 15A is an exemplaryplanar view of the Fin FET device 100A disposed in a core region asshown in FIG. 14. FIG. 15B is an exemplary planar view of the Fin FETdevice 200A disposed in a peripheral region as shown in FIG. 14.

The various embodiments or examples described herein offer severaladvantages over the existing art. For example, by optimizing the heightof the spacer dielectric region and/or the difference between the heightof the dummy gate dielectric region and height of the spacer dielectricregion, it is possible to improve the immunity against the etchingsolution (e.g., dilute-HF and/or aqueous ammonia) for the spacerdielectric region, for example due to surface tension and capillaryeffects. It is also possible to improve gate-to-S/D isolation and devicelife time under hot carrier degradation. In another example, by usingthe surface treatment process to the spacer dielectric region, it ispossible to improve the immunity against the etching solution (e.g.,dilute-HF and/or aqueous ammonia) for the spacer dielectric region.

It will be understood that not all advantages have been necessarilydiscussed herein, no particular advantage is required for allembodiments or examples, and other embodiments or examples may offerdifferent advantages. In one example, although the processes describedwith reference to FIGS. 1A-15B are associated with a semiconductor FETdevice having a fin structure (Fin FET), the processes described withreference to FIGS. 1A-15B may apply to a planar semiconductor devicesuch as a planar MOSFET.

In accordance with one aspect of the present disclosure, a method ofsemiconductor fabrication includes forming a dielectric layer over asubstrate. A first dummy gate structure is formed on the dielectriclayer so that the dielectric layer includes a first gate dielectricregion disposed below and defined by the first dummy gate structure. Aportion of the dielectric layer not included in the first gatedielectric region is etched to form a dielectric etch back regionadjacent the first gate dielectric region. A first spacer element isformed on a portion of the dielectric etch back region and on sidewallsof the first dummy gate structure, and the first spacer element abutsthe dummy gate structure, the portion of the dielectric etch back regionincludes a first spacer dielectric region disposed below and defined bythe first spacer element, and a height of the first gate dielectricregion is greater than the height of the first spacer dielectric region.A first recessed portion is formed in the substrate. A strained materialis selectively grown over the first recessed portion of the substrate toform a first strained recessed region, and the first strained recessregion is adjacent the first spacer dielectric region. The first dummygate structure and the first gate dielectric region are removed to forma first opening. A first gate structure including a gate electrode layerand a gate dielectric layer is formed in the first opening.

In accordance with another aspect of the present disclosure, a method ofsemiconductor fabrication includes forming a first dielectric layer overa substrate. A first dummy gate structure is formed on the firstdielectric layer so that the first dielectric layer comprises a firstgate dielectric region disposed below and defined by the first dummygate structure. A first spacer element is formed on a portion of thefirst dielectric layer, and the first spacer element abuts the firstdummy gate structure, and the portion of the first dielectric layercomprises a first spacer dielectric region disposed below and defined bythe first spacer element. A first recessed portion is formed in thesubstrate. A strained material is selectively grown over the firstrecessed portion of the substrate to form a first strained recessedregion, and the first strained recess region is adjacent the firstspacer dielectric region. The first dummy gate structure is removed. Asecond dielectric layer is formed on the first gate dielectric region.The second dielectric layer and the first gate dielectric region areremoved to form a first opening. A first gate structure including a gateelectrode layer and a gate dielectric layer is formed in the firstopening.

In accordance with another aspect of the present disclosure, asemiconductor device includes a first structure and a second structure.The first structure includes a first gate structure disposed over asubstrate, a first spacer element abutting the first gate structure anda first strained recess region over a recessed portion in the substrateadjacent the first gate structure. The second structure includes asecond gate structure disposed over the substrate, a second spacerelement abutting the second gate structure and a second strained recessregion over a recessed portion in the substrate adjacent the second gatestructure. The first gate structure includes a first gate dielectricregion disposed over the substrate and underlying a first gateelectrode. The second gate structure includes a second gate dielectricregion disposed over the substrate and underlying a second gateelectrode. A first spacer dielectric region is disposed over thesubstrate and underlying the first spacer element and a second spacerdielectric region is disposed over the substrate and underlying thesecond spacer element. A height of the second gate dielectric region isgreater than the height of the second spacer dielectric region.

The foregoing outlines features of several embodiments or examples sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodiments orexamples introduced herein. Those skilled in the art should also realizethat such equivalent constructions do not depart from the spirit andscope of the present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A semiconductor device comprising: a first fieldeffect transistor (FET); and a second FET, wherein: the first FETincludes: a first channel region; an interfacial dielectric layerdisposed on the first channel region; a first gate dielectric layerdisposed on the interfacial dielectric layer; a first gate electrodedisposed on the first gate dielectric layer; a first gate sidewallspacer; and a first spacer dielectric layer disposed under the firstgate sidewall spacer, the second FET includes: a second channel region;a second gate dielectric layer disposed directly on the second channelregion; a third gate dielectric layer disposed on the second gatedielectric layer; a second gate electrode disposed on the third gatedielectric layer; a second gate sidewall spacer; and a second spacerdielectric layer disposed under the second gate sidewall spacer, thefirst spacer dielectric layer is made of a different material than thefirst gate dielectric layer and made of a same material as the secondgate dielectric layer and the second spacer dielectric layer.
 2. Thesemiconductor device of claim 1, wherein the same material is siliconoxide.
 3. The semiconductor device of claim 2, wherein the first gatedielectric layer is made of a same material as the third gate dielectriclayer and includes a high-k dielectric material.
 4. The semiconductordevice of claim 1, wherein a thickness of the second spacer dielectriclayer is smaller than a thickness of the second gate dielectric layer.5. The semiconductor device of claim 4, wherein the thickness of thesecond spacer dielectric layer is same as a thickness of the firstspacer dielectric layer.
 6. The semiconductor device of claim 1, whereinthe second spacer dielectric layer and the second gate dielectric layerare different parts of a continuous layer.
 7. The semiconductor deviceof claim 1, wherein a side face of the first spacer dielectric layer isflush with the first gate sidewall spacer.
 8. The semiconductor deviceof claim 1, wherein: the first FET further includes a third gatesidewall spacer disposed over the first gate sidewall spacer, and nopart of the first spacer dielectric layer is disposed under the thirdgate sidewall spacer.
 9. The semiconductor device of claim 8, wherein:the second FET further includes a fourth gate sidewall spacer disposedover the second gate sidewall spacer, and no part of the second spacerdielectric layer is disposed under the fourth gate sidewall spacer. 10.A semiconductor device including a field effect transistor (FET), theFET comprising: a channel region; a first gate dielectric layer disposedon the channel region; a second gate dielectric layer disposed on thefirst gate dielectric layer; a third gate dielectric layer disposed onthe second gate dielectric layer; a gate electrode disposed on the thirdgate dielectric layer; a first gate sidewall spacer; and a second gatesidewall spacer disposed over the first gate sidewall spacer, wherein:the first gate dielectric layer penetrates under the first gate sidewallspacer, the second and third gate dielectric layers have a U-shape crosssection, respectively.
 11. The semiconductor device of claim 10, whereinthe FET is a transistor of an I/O region.
 12. The semiconductor deviceof claim 10, wherein a thickness the first gate dielectric layer underthe second gate dielectric layer is a same as a thickness of the firstgate dielectric layer under the first gate sidewall spacer.
 13. Thesemiconductor device of claim 10, wherein the first gate dielectriclayer and the second gate dielectric are made of silicon oxide.
 14. Thesemiconductor device of claim 13, wherein the third gate dielectriclayer includes a high-k dielectric material.
 15. The semiconductordevice of claim 10, wherein no part of the first gate dielectric layeris disposed under the second gate sidewall spacer.
 16. The semiconductordevice of claim 10, wherein the first gate sidewall spacer includemultiple layers.
 17. A semiconductor device comprising: a first fieldeffect transistor (FET) located at a core region; and a second FETlocated at an I/O region, wherein: the first FET includes: a firstchannel region; an interfacial dielectric layer disposed on the firstchannel region; a first gate dielectric layer disposed on theinterfacial dielectric layer; a first gate electrode disposed on thefirst gate dielectric layer; a first gate sidewall spacer; and a firstspacer dielectric layer disposed under the first gate sidewall spacer,the second FET includes: a second channel region; a second gatedielectric layer disposed directly on the second channel region; a thirdgate dielectric layer disposed on the second gate dielectric layer; afourth gate dielectric layer disposed on the third gate dielectriclayer; a second gate electrode disposed on the third gate dielectriclayer; a second gate sidewall spacer; and a second spacer dielectriclayer disposed under the second gate sidewall spacer, the first spacerdielectric layer is made of a different material than the first gatedielectric layer, and the second spacer dielectric layer and the secondgate dielectric layer are different parts of a continuous layer.
 18. Thesemiconductor device of claim 17, wherein the first, third and fourthgate dielectric layers have a U-shape cross section, respectively. 19.The semiconductor device of claim 17, wherein a voltage applied to thesecond FET is higher than a voltage applied to the first FET.
 20. Thesemiconductor device of claim 17, wherein the first spacer dielectriclayer is made of a same material as the second gate dielectric layer andthe second spacer dielectric layer.